As the use of power control IC becomes more widespread and its trend proceeds from a single-function IC device such as the voltage regulator and voltage detector to an integrated device such as a large-scale IC, various problems have been encountered as to device requirements.
That is, in addition to the conventional capabilities of driving and controlling circuits at high voltages and large currents, the power control IC has to incorporate various components on board on one single substrate, such as VLSI (very large-scale integration) logical circuits, memory, and CPU (central processing unit).
For use in properly handling high voltages and large currents, DMOS (double-diffused metal-oxide semiconductor) transistor is one of the most important driver devices, and LDMOS (lateral DMOS) transistor in particular is known to be quite suitable for on-board mounting in combination with VLSI circuit.
The LDMOS (lateral DMOS) transistor is characterized primarily by its figure of merit such as transistor withstand voltage and on-resistance.
The transistor withstand voltage is a factor of primary importance for use in power control IC. In conformity with this withstand voltage, the fundamental structure of the transistor is largely determined in terms of (1) the concentration, and the depth of impurities to be disposed in junction regions, and (2) the thickness of gate oxide films, for example.
The on-resistance is a parameter indicative of the capability of driving current per unit area, and its value as small as possible is preferable for the LDMOS transistor.
In concurrence with the abovementioned trend of increasing degree of integration and high voltage capability, the application of the device has widened also to the area of onboard electronic equipments. In that area of the application, severe device requirements have to be fulfilled particularly in harsh electrical environment for controlling ESD (electrostatic discharge) and noises.
In the case when statically-charged human body or object comes into contact with an electrostatic discharge sensitive device, there is a possibility that the electrostatic discharge could be drained through sensitive circuitry in the device. If the electrostatic discharge possesses sufficient energy, damage could occur in the device due to localized overheating. Generally, devices with finer geometries are more susceptible to damage from ESD.
Integrated circuits are therefore sensitive to ESD to some degree. One method employed to protect the circuits is to incorporate a protective resistor between an internal device element and an output terminal to decrease the potential.
This method, however, is not so advantageous for the abovementioned LDMOS transistor which inherently has a low on-resistance, and protective diodes, therefore, have been used previously to protect the elements included in power ICs.
Because of high withstand voltages required for the protective diode, sufficient capabilities of ESD protection can not be achieved by a parasitic diode, but a specific diode has to be formed having a high withstand voltage. This generally forces to set aside relatively large area on the device for forming the diode, which may give rise to an increase in device costs.
In regard to device characteristics of the protective diode, it is desirable for its breakdown voltage to be equal to or higher than a rated voltage of the diode, and equal to or lower than a breakdown voltage of the high withstand voltage device. Also desired is the diode structure which can prevent junction breakdown during extracting the electric charges.
In order to insure such characteristics, the protective diode has been previously formed having impurity diffusion layers with an impurity concentration specifically designed for the diode.
As a result, the process becomes more complicated and the number of process steps increases. Moreover, the diode takes up a relatively large portion of the area of semiconductor device, which results in an undesirable increase in chip size.
One method for obviating the abovementioned difficulties has been disclosed, which will be described briefly herein below.
According to the disclosure, an N-type high voltage region is formed on a P-type semiconductor substrate, an N-type guard ring region is formed on the surface of the semiconductor substrate in the vicinity of the periphery of the N-type well region, and a P-type substrate pickup region is formed opposing to the guard ring region also on the surface of the semiconductor substrate.
Consisting of the thus formed N-type guard ring region, N-type high voltage region, P-type semiconductor substrate, and P-type substrate pickup region, a protective diode is formed. In addition, a breakdown voltage of the protective diode can be adjusted by changing the distance between the guard ring region and the substrate pickup region (Japanese Laid-Open Patent Application No. 2003-17694, for example).
FIG. 20 is a cross-sectional view illustrating a known protective diode, in which there formed are an N-type well region (NW) 104 on a P-type semiconductor substrate (Psub) 102, an N-type guard ring region (N+) 167 on the surface of the semiconductor substrate 102 inside the N-type well region (NW) 104, and a P-type substrate pickup region (P+) 169 on the surface of the semiconductor substrate 102 so as to oppose to the guard ring region 167.
In the method disclosed in the Application No. 2003-17694, however, a drawback with this attempted device structure is that variations in the location resulted from mask positioning, which is performed on the guard ring region 167 and well region 104, affect considerably to the variation of resulting breakdown voltage of the protective diode, and that the withstand voltage is hard to be brought particularly to 40V or lower in a stable (or reproducible) manner.
Although the guard ring region 167 and the substrate pickup region 169 are both formed stably with the self-alignment technique using LOCOS oxide film, the location of the well region 104 may be susceptible to variations through the process step of mask positioning.
Since the degree of overlap between the guard ring region 167 and the well region 104 has a considerable influence on breakdown voltages of the protective diode, the fluctuation in ESD tolerance caused by the variations through mask positioning is a difficulty yet to be solved in spite of the device structure disclosed in the Application No. 2003-17694.
Since the breakdown voltage lower than the rated voltage is not allowed for a protective diode, the breakdown voltage has to be set higher in practice when the variation of the location of the well region 2 through mask positioning is considered. This in turn may bring the breakdown voltage of the protective diode higher than that of the high withstand voltage device. Thus, a further difficulty results in ensuring adequate ESD tolerance.